Correct option is B
Question
A 4-stage pipeline has the stage delay as 150, 120, 160 and 140 ns respectively. Registers that are used between the stages have delay of 5 ns. Assuming constant locking rate, the total time required to process 1000 data items on this pipeline is:
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EnglishSimilar Questions
- 1)
What does “Amdahl’s Law” describe in the context of parallel processing?
- 2)The right sequence of suboperations that are performed in the arithmetic pipeline is-
A. Align the mantissas
B. Add or subtract the mantissas
C. Normalize the result
D. Compare the exponents
Choose the correct answer from the options given below: - 3)Consider a pipeline unit for fixed-point multiplication of 8-bit integers. Arrange the following stages in a correct sequence.
Stage A: Consists of two CSAs and it merges four numbers from the previous stage.
Stage B: is a CPA, which adds up the two numbers.
Stage C: is made up of two levels of four CSAs.
Stage D: Generates eight partial products.
Choose the correct answer from the options given below: - 4)A non-pipeline system takes 50ns to process a task. The same task can be processed in six-segment pipeline with a clock cycle of 10ns. Determine approximately the speedup ratio of the pipeline for 500 tasks.
- 5)
Which of the following statements with respect to K-segment pipelining are true?
(A) Maximum speedup that a pipeline can provide is k theoretically.
(B) It is impossible to achieve maximum speedup k in k-segment pipeline.
(C) All segment in pipeline take the same time in computation.
Choose the correct option: - 6)A 4-stage pipeline has the stage delay as 150, 120, 160 and 140 ns respectively. Registers that are used between the stages have delay of 5 ns. Assuming constant locking rate, the total time required to process 1000 data items on this pipeline is:
- 7)A CPU has a 5-stage pipeline with the following stages Fetch (F), Decode (D), Execute (E), Memory (M) and Write-back (W). Each stage takes one clock cycle to complete. Assume there are no pipeline stalls and the pipeline is initially empty. How many clock cycles are required to complete the execution of 10 instructions?
- 8)A vector processor with 16 lanes can perform an operation on 1024 elements with each operation taking 5 clock cycles. How many cycles are needed to complete the operation?
- 9)
What does “Amdahl’s Law” describe in the context of parallel processing?
- 10)The right sequence of suboperations that are performed in the arithmetic pipeline is-
A. Align the mantissas
B. Add or subtract the mantissas
C. Normalize the result
D. Compare the exponents
Choose the correct answer from the options given below:
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12 months
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UGC NET Paper 1 Mock Test June 2026
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Similar Questions
- 1)
What does “Amdahl’s Law” describe in the context of parallel processing?
- 2)The right sequence of suboperations that are performed in the arithmetic pipeline is-
A. Align the mantissas
B. Add or subtract the mantissas
C. Normalize the result
D. Compare the exponents
Choose the correct answer from the options given below: - 3)Consider a pipeline unit for fixed-point multiplication of 8-bit integers. Arrange the following stages in a correct sequence.
Stage A: Consists of two CSAs and it merges four numbers from the previous stage.
Stage B: is a CPA, which adds up the two numbers.
Stage C: is made up of two levels of four CSAs.
Stage D: Generates eight partial products.
Choose the correct answer from the options given below: - 4)A non-pipeline system takes 50ns to process a task. The same task can be processed in six-segment pipeline with a clock cycle of 10ns. Determine approximately the speedup ratio of the pipeline for 500 tasks.
- 5)
Which of the following statements with respect to K-segment pipelining are true?
(A) Maximum speedup that a pipeline can provide is k theoretically.
(B) It is impossible to achieve maximum speedup k in k-segment pipeline.
(C) All segment in pipeline take the same time in computation.
Choose the correct option: - 6)A 4-stage pipeline has the stage delay as 150, 120, 160 and 140 ns respectively. Registers that are used between the stages have delay of 5 ns. Assuming constant locking rate, the total time required to process 1000 data items on this pipeline is:
- 7)A CPU has a 5-stage pipeline with the following stages Fetch (F), Decode (D), Execute (E), Memory (M) and Write-back (W). Each stage takes one clock cycle to complete. Assume there are no pipeline stalls and the pipeline is initially empty. How many clock cycles are required to complete the execution of 10 instructions?
- 8)A vector processor with 16 lanes can perform an operation on 1024 elements with each operation taking 5 clock cycles. How many cycles are needed to complete the operation?
- 9)
What does “Amdahl’s Law” describe in the context of parallel processing?
- 10)The right sequence of suboperations that are performed in the arithmetic pipeline is-
A. Align the mantissas
B. Add or subtract the mantissas
C. Normalize the result
D. Compare the exponents
Choose the correct answer from the options given below:
