A CPU has a 5-stage pipeline with the following stages Fetch (F), Decode (D), Execute (E), Memory (M) and Write-back (W). Each stage takes one clock cycle to complete. Assume there are no pipeline stalls and the pipeline is initially empty. How many clock cycles are required to complete the execution of 10 instructions?

In a 5-stage pipeline, the number of cycles to complete n instructions can be calculated as:
1. Initial Pipeline Filling: Requires 5 cycles (one for each stage).
2. Remaining Instructions: Each new instruction completes in 1 additional cycle.
Total Cycles = 5 + (10 − 1) = 5 + 9 = 14
Information Booster:
· Pipeline Stages:
· Fetch (F): Retrieves instruction from memory.
· Decode (D): Decodes the instruction.
· Execute (E): Executes the instruction.
· Memory (M): Accesses memory if needed.
· Write-back (W): Writes results back to register.
Additional Knowledge:
Without any stalls, pipelines increase instruction throughput but not necessarily the execution speed of individual instructions.