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Which of the following can be used to prevent race around condition in digital logic circuit?
Question

Which of the following can be used to prevent race around condition in digital logic circuit?

A.

Full adder

B.

AND gate

C.

Master slave JK flip-flop

D.

Shift register

Correct option is C


Master slave JK flip-flop: The master-slave JK flip-flop configuration is specifically designed to prevent the race-around condition. It uses two JK flip-flops in a master-slave arrangement, where the master flip-flop is enabled on the clock's rising edge and the slave flip-flop is enabled on the falling edge. This ensures that the inputs are stable and the output changes only once per clock cycle, preventing race-around conditions.

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