The instructions
ADD R1, A, B
ADD R2, C, D
MUL X, R1, R2
evaluates the X = (A + B) * (C + D) in which of the following?

The computer needs to process each instruction with the following sequence of steps:
A. Calculate the effective address
B. Fetch the instruction from memory
C. Decode the instruction
D. Fetch the operands from memory
E. Execute the instruction
Choose the correct answer from the options given below:

Which of the following is not an example of pseudo-instruction?

Given below are two statements:
Statement I: CISC computers have a large number of addressing modes.
Statement II: In RISC machines, memory access is limited to load and store instructions.
In light of the above statements, choose the correct answer from the options given below:

Given below are two statements:
Statement I: Consider 20-bit 'Branch' microinstruction code format given below:

F1, F2, F3: Micro-operation fields
CD: Condition for branching
BR: Branch field
AR: Address field
Statement II: Instruction represented in the above format can perform branch in 4 conditions.
In the light of the above statements, choose the most appropriate answer from the options given below:

For multiprocessor system, interconnection network-cross bar switch is an example of:

The instruction LD ADR(X) which is equivalent to AC ← M[ADR + XR] is in :

The instructions
ADD R1, A, B
ADD R2, C, D
MUL X, R1, R2
evaluates the X = (A + B) * (C + D) in which of the following?

The computer needs to process each instruction with the following sequence of steps:
A. Calculate the effective address
B. Fetch the instruction from memory
C. Decode the instruction
D. Fetch the operands from memory
E. Execute the instruction
Choose the correct answer from the options given below: