How does the triggering mechanism differ between a latch and a flip-flop in digital circuits?

Correct option is C

​$$\textbf{Explanation} \\[6pt]\bullet \ \textbf{Latches} \text{ respond to the } \textit{level} \text{ (HIGH or LOW) of an enable or clock signal.} \\[2pt]\quad \text{They remain transparent as long as the enable level is active.} \\[6pt]\bullet \ \textbf{Flip-flops} \text{ change their output only on a } \textit{specific clock edge} \\[2pt]\quad \text{(rising edge or falling edge).} \\[8pt]\text{Thus, the key distinction in triggering is:} \\[6pt]\text{Latch } \rightarrow \text{ Level-triggered} \qquad \text{Flip-flop } \rightarrow \text{ Edge-triggered}$$​​