A 4-bit serial-in parallel-out shift register is initially set to 1111. The data 1010 is applied to the input. After 3 clock cycles the output will be:

Access ‘DFCCIL Technical’ Mock Tests with

• 60000+ Mocks and Previous Year Papers
• Unlimited Re-Attempts
• Personalised Report Card
• 500% Refund on Final Selection
• Largest Community

368k+ students have already unlocked exclusive benefits with Test Prime!