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Quiz Electronics Engineering 24 July 2020

Quiz Electronics Engineering
Exam: NIC
Topic: Miscellaneous
Date: 24/07/2020

Each Question carries 1 Mark
Negative Marking: 1/4
Time: 10 Minutes

Q1. Increased pulse width in the flat top sampling leads to
(a) attenuation of high frequencies in reproduction
(b) attenuation of low frequencies in reproduction
(c) greater aliasing errors in reproduction
(d) no harmful effects in reproduction

Q2. A semiconductor in its purest form is called …
(a) insulator
(b) superconductor
(c) intrinsic semiconductor
(d) extrinsic semiconductor

Q3. A charge Q is enclosed by a Gaussian spherical surface of radius R. If R is doubled then the outward flux is
(a) doubled
(b) increased four times
(c) reduced to a quarter
(d) remains unaltered

Q4. How many address lines are needed to address each memory location in a 1024 × 8 memory chip?
(a) 10
(b) 11
(c) 8
(d) 12

Q5. In binary numbers, shifting the binary decimal point one place to the right
(a) multiplies by 2
(b) divides by 2
(c) decreases by 10
(d) increases by 10

Q6. Norton’s Theorem is
(a) The same as Thevenin’s theorem
(b) Converse of Thevenin’s theorem
(c) Cannot say
(d) Same as Newton’s theorem

Q7. The period of the function cos[π/8(t-1)] is
(a) 1/8 s
(b) 16 s
(c) 8 s
(d) 1/16 s

Q8. Laplacian of a scalar function V is
(a) Gradient of V
(b) Divergence of V
(c) Gradient of the gradient of V.
(d) Divergence of the gradient of V.

Q9. How can the channel width in a JFET be controlled?
(a) by the length of the drain
(b) by the length of the source
(c) by two back-biased pn junction
(d) by the length of the drain by the lengths of both source and drain

Q10. The input of an ac circuit having p.f. of 0.8 lagging is 20 kVA. The power drawn by the circuit is____ kW.
(a) 16
(b) 15
(c) 12
(d) 8


S1. Ans.(a)
Sol. Flat top sampling of low pass signal gives the spectrum of sinc function with attenuated amplitude of high frequency components. This affect is called Aperture effect. As there is increase in pulse width, there will be more loss in high frequency components.

S2. Ans.(c)
Sol. Intrinsic semiconductor is a material which do not have any impurity material mixed in it. Hence, Intrinsic semiconductor is called Pure semiconductor.

S3. Ans.(d)
Sol. Flux is equal to the total charges enclosed in a Gaussian spherical surface, it does not depend upon the radius of Gaussian spherical surface.

S4. Ans.(a)
Sol. 1024 × 8 = 2^10 × 8
Hence, 10 address lines are needed with each address line of 4-bits.

S5. Ans.(a)
Sol. Shifting the binary decimal point one place to the right shows the increment of the number. So. The number increases and it is done by multiplying by 2.
Before Shifting,

After Shifting one decimal point to the right we get,

S6. Ans.(b)
Sol. In Norton’s equivalent Circuit, Norton resistance is connected in parallel with the Norton Current source but in Thevenin’s equivalent circuit, Thevenin resistance is connected in series with the Thevenin Voltage source. Hence, Norton’s theorem is converse of Thevenin’s theorem.

S7. Ans.(b)
Sol. Given:
f(t) = cos[π/8(t-1)]
We know that, Period = 2π/ω for any sinusoidal function like cosωt
After comparing f(t) with standard sinusoidal signal cosωt.
We get, ω = π/8
So, Period = 2π/(π/8) = 2 x 8 = 16 s

S8. Ans.(d)
Sol. Laplacian equation is ∇^2 V = ∇.∇V
Laplacian of a scalar field V results in the divergence of gradient of V.

S9. Ans.(c)
Sol. The channel width of JFET can be controlled by Gate to Source voltage. On applying the reverse bias voltage to the gate, the depletion width of PN junction increases so the net channel width decreases due to penetration of depletion layer in the channel. So, two back-biased pn junction controls the channel width of a JFET.

S10. Ans.(a)
Sol. Given:
cosϕ = 0.8
Input power(V.I) = 20 kVA
Power drawn by the circuit is
⇒ P = V.I cosϕ
⇒ P = 20 × 0.8 kW
So, P = 16 kW

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