Engineering Jobs   »   Quiz Electronics Engineering 31 March 2020

Quiz Electronics Engineering 31 March 2020

Quiz Electronics Engineering
Exam: NIC
Topic: Miscellaneous
Date: 31/03/2020

Each Question carries 1 Mark
Negative Marking: 1/4
Time: 10 Minutes

Q1. Which of the following digital modulation can be decoded non-coherently?
(a) BFSK
(b) QAM
(c) BPSK
(d) APSK
L1 Difficulty 2
QTags Communication Engineering
QCreator Vikram Kumar

Q2. Which of the following digital devices require an external refresh circuit?
(a) SRAM
(b) FLASH Memory
(d) DRAM
L1 Difficulty 3
QTags Operating System
QCreator Vikram Kumar

Q3. Which of the following digital integrated circuit cannot be used as wired logic connections?
(a) Open Collector TTL gate
(b) Totem-pole TTL gate
(c) Emitter coupled logic
(d) Totem-pole output with 3-stage gate
L1 Difficulty 4
QTags Digital Electronics
QCreator Vikram Kumar

Q4. Which of the following is false for a Thyristor?
A. Thyristor is a majority-carrier device.
B. The forward-bias portion of Thyristor’s i-v characteristics has two stable operating regions.
C. The forward-bias portion of Thyristor’s i-v characteristics has one stable operating region.
D. The negative gate current turns off the Thyristor.
(a) A,D
(b) B,C,D
(c) A,C,D
(d) A,B
L1 Difficulty 3
QTags Power electronics (electrical engineering)
QCreator Vikram Kumar

Q5. Of the following sort algorithms, which has execution time that is least dependent on initial ordering of the input?
(a) Merge Sort
(b) Quick Sort
(c) Inserting Sort
(d) Selection Sort
L1 Difficulty 4
QTags Computer
QCreator Vikram Kumar

Q6. What is the availability of the software with the following reliability figures. Mean Time Between Failures (MTBF) is 20 days and Mean Time To Repair (MTTR) is 20 hours.
(a) 50%
(b) 24%
(c) 96%
(d) 90%
L1 Difficulty 3
QTags Software Engineering
QCreator Vikram Kumar

S7. Statements associated with registers of a CPU are given. Identify the FALSE statement.
(a) The Program Counter holds the memory address of the instruction in execution.
(b) Only Opcode is transferred to the Control Unit.
(c) An instruction in the Instruction Register consists of the Opcode and the Operand.
(d) The value of the program Counter is incremented by 1 once its value has been read to the Memory Address Register.
L1 Difficulty 2
QTags Computer Organization & Microprocessor
QCreator Vikram Kumar

Q8. If the Array A contains the items 10, 4, 7, 23, 67, 12 and 5 in that order, what will be the resultant Array A after third pass of Insertion Sort?
(a) 67, 12, 10, 5, 4, 7,23
(b) 4, 7,10, 23, 67,12, 5
(c) 4, 5, 7,67, 10, 12, 23
(d) 10, 7, 4, 67, 23, 12, 5
L1 Difficulty 2
QTags Data Structure
QCreator Vikram Kumar

Q9. Avalanche effect in Cryptography refers to
(a) Large changes in cipher text when the keyword is changed minimally.
(b) Large impact of keyword change to length of the cipher text.
(c) Large changes in cipher text when the plain text is changed.
(d) None of the above
L1 Difficulty 3
QTags Networking Security
QCreator Vikram Kumar

Q10. Properties of ‘DELETE’ and ‘TRUNCATE’ commands indicate that
(a) After the execution of ‘DELETE’ and ‘TRUNCATE’ operation retrieval is easily possible for the lost data.
(b) After the execution of ‘DELETE, operation, COMMIT and ROLLBACK statements can be performed to retrieve the lost data, while TRUNCATE do not allow it.
(c) After the execution of ‘DELETE’ and ‘TRUNCATE’ operation no retrieval is possible for the lost data.
(d) None of the above
L1 Difficulty 3
QCreator Vikram Kumar


S1. Ans.(a)
Sol. Binary Frequency Shift Key is decoded non coherently.

S2. Ans.(d)
A DRAM stores data in the form of charge on capacitor. A capacitor discharges after certain interval of time. To maintain the charge across the capacitor it is recharged or refreshed at periodic interval.
A FLASH memory retains data in the absence of power supply.
EEPROM is a read-only memory whose contents can be erased and reprogrammed using a pulsed voltage.
A SRAM stores data bits in its memory as long as power is supplied to it. It is used for computer’s cache memory.

S3. Ans.(b)
A wired logic connection is a logic gate that implements Boolean expression using only passive components such as diodes and resistors. It can create an AND or an OR gate. The limitations are the inability to create a NOT gate and the lack of level restoration.
An Open Collector TTL gate is an integrated circuits (IC), which behaves like a switch either connected to ground or disconnected. It is used in performing wired logic.
Totem-pole output with 3-stage gate has an active pull up circuit in the output of the Gate which results in reduction of propagation delay. It has 3-state output. It allows a direct wire connection of many outputs.
ECL has also wired logic connection.
In Totem-pole TTL gate output wired-logic connection is not allowed. Because the current flowing will increase and also the output will not stay low if one of the outputs of the totem pole is low.

S4. Ans.(c)

S5. Ans.(a)
When inputs are already sorted, Insertion Sort gives O(n) time.
When inputs are almost sorted, Quick Sort gives O(n2) time.
Merge Sort is independent of initial ordering and always gives O(n logn).
Selection Sort gives O(n2) always but if elements are always sorted, number of swaps will be less.

S6. Ans.(c)
Sol. Given:
MTBF = 20 days = 20 x 24 hours = 480 hrs.
MTTR = 20 hrs.
Now, Software Availability = MTBF/((MTBF+MTTR)) *100
= 480/((480 + 20)) *100 = 480/500 *100 = 96%

S7. Ans.(a)
Option (a): PC holds the address of the next instruction to be fetched and Memory Address Register holds the address of the instruction being executed.
Option (b): Control Unit needs only the Opcode of the instruction. The other information Addressing Mode and the Operands are required by the ALU .
Option (c): Instruction Register (IR) is the register that holds the instruction which includes opcode and operand. An instruction is fetched when loaded in IR.
Option (d): MAR holds the address of the current instruction in execution. When the contents of PC are loaded into MAR, PC is incremented by 1 to direct to the address of next instruction.

S8. Ans.(b)
Given Array: 10, 4, 7, 23, 67, 12, 5
After 1st pass: 4, 10, 7, 23, 67, 12, 5
After 2nd pass: 4, 7, 10, 23, 67, 12, 5
After 3rd pass: 4, 7, 10, 23, 67, 12, 5

S9. Ans.(a)
Sol. In cryptography in case of high-quality block ciphers, if even tiny changes in the input keyword or plaintext occur, the ciphertext is changed drastically.

S10. Ans.(b)
S. No. Delete Truncate
01 Commit and Rollback possible after delete operation. After Truncate operation Rollback and Commit operation can’t be performed
02 Can’t reset identity of table. identity of table is reset.
02 locks row of the table. locks the entire table.
04 DML command DDL command
05 Trigger is fired. Trigger is not fired.

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